
`include "common_header.verilog"

//  *************************************************************************
//  File : tsm40_txtsi
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited.
//  Copyright (c) 2014 MoreThanIP.com, Germany
//  Designed by : Daniel Koehler
//  support@morethanip.com
//  *************************************************************************
//             Ethernet MAC Core
//  *************************************************************************
//  Description: Latch timestamp and id for transmitted frames.
//  Version    : $Id: tsm40_txtsi.v,v 1.1 2014/06/05 12:20:18 ts Exp $
//  *************************************************************************

module tsm40_txtsi (

   reset_txclk,
   xgmii_txclk,
   xgmii_txclk_ena,
   frc_in_tx,
   rden_int_eop,
   tx_stat_id,
   tx_stat_ts_frm,
   tsv_stat_val,
   tsv_stat_gpause,
   tx_ts_val_int,
   tx_ts_int,
   tx_ts_id_int,
   tx_ts_frm_out);

`include "mtip_40geth_pack_package.verilog"

input   reset_txclk;            //  Active High reset for xgmii_txclk domain
input   xgmii_txclk;            //  XGMII transmit clock
input   xgmii_txclk_ena;        //  XGMII transmit Clock Enable
input   [TS_WIDTH-1:0] frc_in_tx; //  current time synchronous to tx clock domain
input   rden_int_eop;           //  Transmit reads last word from FIFO => status valid
input   [TSID_WIDTH-1:0] tx_stat_id; //  frame identifier
input   tx_stat_ts_frm;         //  store timestamp command to tx
input   tsv_stat_val;           //  Transmit Statistic Vector Valid.
input   tsv_stat_gpause;        //  Transmit Statistic Vector pause generated status bit.
output   tx_ts_val_int;         //  tx_ts_xxx valid indication
output   [TS_WIDTH-1:0] tx_ts_int;      //  transmit timestamp
output   [TSID_WIDTH-1:0] tx_ts_id_int;    //  frame identifier
output   tx_ts_frm_out;         //  Transmit Timestamp Frame

reg     tx_ts_val_int; 
reg     [TS_WIDTH-1:0] tx_ts_int; 
reg     [TSID_WIDTH-1:0] tx_ts_id_int; 
reg     tx_ts_frm_out; 

//  store data from FIFO when frame read starts
//  -------------------------------------------
always @(posedge reset_txclk or posedge xgmii_txclk)
   begin : tsrxp
   if (reset_txclk == 1'b 1)
      begin
      tx_ts_id_int  <= {TSID_WIDTH{1'b 0}};	
      tx_ts_frm_out <= 1'b 0;	
      end
   else
      begin
        //  CLOCK ENABLE
      if (xgmii_txclk_ena == 1'b 1)
         begin
         if (rden_int_eop == 1'b 1)
            begin
            tx_ts_id_int  <= tx_stat_id;	
            tx_ts_frm_out <= tx_stat_ts_frm;	
            end

         end
      end
   end

//  capture timestamp
always @(posedge reset_txclk or posedge xgmii_txclk)
   begin : tc
   if (reset_txclk == 1'b 1)
      begin
      tx_ts_int <= {TS_WIDTH{1'b 0}};	
      tx_ts_val_int <= 1'b 0;
      end
   else
      begin
      if (tsv_stat_val == 1'b 1)       // is a pulse not using clock enable!
         begin
            tx_ts_int <= frc_in_tx;	
         end

        //  indicate frame transmission completed at same time as statistics Vector, except if it was a generated pause frame.

        tx_ts_val_int <= tsv_stat_val & ~tsv_stat_gpause; 

      end
   end


endmodule // module tsm40_txtsi

